Active inductors have become standard building blocks for many applications by its recon gurability and reduced silicon area. However, the inductance variation over temperature is a main circuits' limitation in harsh environments. This paper presents a novel temperature analysis of a general architecture of active inductors, obtaining an optimal conductance value to minimize inductance variation over temperature. Based on the m /I D and sensitivity analysis, temperature variation result highlights that, even if its counter intuitive to bias transistors in weak inversion, a low inductance variation of 139 ppm/ °C.