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Conference Papers Year : 2006

A hardware efficient 3-bit second-order dynamic element matching circuit clocked at 300MHz

Abstract

A robust and hardware efficient dynamic element matching (DEM) algorithm is developed and used to design a 4th-order bandpass (BP) mismatch-shaping circuit, moved inside the feedback loop of a 6th-order bandpass continuous-time delta-sigma modulator. This algorithm is based on a shortened tree-structured scheme (STDEM) which can assure a stable high order mismatch-shaping with a modest circuit volume. The modulator has a 3-bit quantizer and 8 thermometric feedback DAC's cells. The designed DEM's circuits is simulated in 0.35μ- CMOS which can be clocked up to 300-MHz. The mismatch error floor is decreased of about 35dB in the band of interest. Its related circuit occupies of about 0.22mm2 area.
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Dates and versions

hal-00257788 , version 1 (20-02-2008)

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Esmaeil Najafi Aghdam, Philippe Benabes. A hardware efficient 3-bit second-order dynamic element matching circuit clocked at 300MHz. International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.2977-2980, ⟨10.1109/ISCAS.2006.1693250⟩. ⟨hal-00257788⟩
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