DESIGN OF A 3 GHz 6TH ORDER DELTA-SIGMA MODULATOR IN A 0.2 μm GaAs TECHNOLOGY - CentraleSupélec Access content directly
Conference Papers Year : 2006

DESIGN OF A 3 GHz 6TH ORDER DELTA-SIGMA MODULATOR IN A 0.2 μm GaAs TECHNOLOGY

Abstract

This paper presents the design of a monobit 6th order delta-sigma modulator in a GaAs 0.2 μm technology. The central frequency is 750 MHz and the sampling frequency is 3 GHz. The reached resolution is 10.5 bits over a 10 MHz bandwith. The modulator operates from ± 5 V power supplies and consumes 5.7 W. Each block of the modulator is presented at transistor level. Two drawbacks are pointed out: low pass terms of Gm-LC resonators and the lowpass characteristic of the adder. Two solutions are proposed. Finally, simulation results of the complete modulator are given.
Fichier principal
Vignette du fichier
IASTED_CSS_531-129.pdf (331.69 Ko) Télécharger le fichier
Origin Files produced by the author(s)
Loading...

Dates and versions

hal-00258577 , version 1 (22-02-2008)

Identifiers

  • HAL Id : hal-00258577 , version 1

Cite

Emilie Avignon, Sylvie Guessab, Richard Kielbasa, Jean-Marc Guebhard, Nicolas Fel, et al.. DESIGN OF A 3 GHz 6TH ORDER DELTA-SIGMA MODULATOR IN A 0.2 μm GaAs TECHNOLOGY. International Conference on Circuits, Signal and Systems, Nov 2006, San Francisco, United States. pp. 205-210. ⟨hal-00258577⟩
96 View
286 Download

Share

Gmail Mastodon Facebook X LinkedIn More