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Conference Papers Year : 2010

A clock network of distributed ADPLLs using an asymmetric comparison strategy

Abstract

In this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.
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Dates and versions

hal-00520988 , version 1 (24-09-2010)

Identifiers

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A. Korniienko, Eric Colinet, Gérard Scorletti, Eric Blanco, Dimitri Galayko, et al.. A clock network of distributed ADPLLs using an asymmetric comparison strategy. IEEE International Symposium on Circuit and Systems (ISCAS'10), May 2010, Paris, France. pp.3212-3215, ⟨10.1109/ISCAS.2010.5537932⟩. ⟨hal-00520988⟩
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