A 2GHz CMOS DCO with optimized architecture for high speed clocking - CentraleSupélec Access content directly
Conference Papers Year : 2011
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hal-00631096 , version 1 (11-10-2011)

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  • HAL Id : hal-00631096 , version 1

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Eldar Zianbetov, Mohammad Javidan, François Anceau, Dimitri Galayko, Eric Colinet, et al.. A 2GHz CMOS DCO with optimized architecture for high speed clocking. International Symposium on Circuits and Systems (ISCAS'11), May 2011, Rio de Janeiro, Brazil. pp.2845-2848. ⟨hal-00631096⟩
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