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Journal Articles IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications Year : 2012

Synchronization Analysis of Networks of Self-sampled All-Digital Phase-Locked Loops

Abstract

This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the whole network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging. Under simple assumptions, these networks of so-called "self-sampled" all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. The main contribution of this paper is a simple design rule that must be met by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific (but important) class of SS-ADPLLs. A synthesis of the different approaches that have been conducted in the study of the synchronization of SS-ADPLLs is also done.
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Dates and versions

hal-00695843 , version 1 (05-10-2012)

Identifiers

Cite

Jean-Michel Akre, Jérôme Juillard, Dimitri Galayko, Eric Colinet. Synchronization Analysis of Networks of Self-sampled All-Digital Phase-Locked Loops. IEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, 2012, 59 (4), pp.708-720. ⟨10.1109/TCSI.2011.2169745⟩. ⟨hal-00695843⟩
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