The conception of analog and mixed-signal functions requires great effort because the complex analog parts should be recursively optimized based not only on system-level requirements but also on technological limitations and imperfections. High-level behavioral models used for chip-level simulations can be employed using multi-domain hardware description languages (HDL), but they are usually manually written and lack technological characteristics. Moreover, automatic resizing and optimization at the transistor level are very limited, and the behavioral models cannot be re-adjusted to changes at the transistor level. In this paper, we present an efficient design methodology implying the automatic optimization of cells at the transistor level using a modified Bayesian Kriging approach and the extraction of robust analog macro-models, which can be directly regenerated during the optimization process. Coherent results were obtained when using the proposed methodology for the conception of a sixthorder continuous-time (CT) Sigma-Delta (ΣΔ) modulator.