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Journal Articles IET Circuits, Devices & Systems Year : 2013

High-loop-delay sixth-order bandpass continuous-time sigma-delta modulators

Abstract

This study focuses on the design of high-loop-delay modulators for parallel sigma-delta conversion. Parallel converters, allowing a global low oversampling ratio, consist of several bandpass modulators with adjacent central frequencies. To ensure the global performance, the noise transfer function (NTF) of each modulator must be adjusted regarding its central frequency. In this thematic a new topology of sixth-order modulators based on weighted-feedforward techniques is developed. This topology offers an adequate control of the NTF at each central frequency by simple means. Additive signal paths are moreover proposed to obtain an auto-filtering signal transfer function. An optimisation method is also developed to calculate the optimised coefficients of the modulators at different central frequencies. The main concerns are improving the stability and reducing the sensitivity of the continuous-time circuit to analogue imperfections. This is essential for parallel conversion since, in each channel, the modulator works at a central frequency which differs from the fourth of the sampling frequency. The performance of the optimised modulator is compared with its discrete-time counterpart with good argument.

Domains

Electronics
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Dates and versions

hal-00932076 , version 1 (22-09-2014)

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Mohammad Javidan, Jérome Juillard, Philippe Benabes. High-loop-delay sixth-order bandpass continuous-time sigma-delta modulators. IET Circuits, Devices & Systems, 2013, 7 (6), pp.305 - 312. ⟨10.1049/iet-cds.2011.0313⟩. ⟨hal-00932076⟩
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