Hardware/Software codesign guidelines for System on Chip FPGA-based sensorless AC drive applications - CentraleSupélec Access content directly
Journal Articles IEEE Transactions on Industrial Informatics Year : 2013

Hardware/Software codesign guidelines for System on Chip FPGA-based sensorless AC drive applications

Abstract

This paper aims to provide Hardware/Software (Hw/Sw) codesign guidelines for system-on-chip field-programmable gate array-based sensorless ac drive applications. Among these guidelines, an efficient Hw/Sw partitioning procedure is presented. This Hw/Sw partitioning is performed taking into account both the control requirements (bandwidth and stability margin) and the architectural constraints (e.g., available area, memory, and hardware multipliers). A nondominated sorting genetic algorithm (NSGA-II) is used to solve the corresponding multi-objective optimization problem. The proposed Hw/Sw partitioning approach is then validated on a sensorless control algorithm for a synchronous motor based on an extended Kalman filter. Among the nondominated implementation solutions supplied by the NSGA-II, those that are considered as the most interesting are synthesized. Their time/area performances after synthesis are compared with success to their predictions. In addition, one of these optimal solutions is also tested on an experimental setup.
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Dates and versions

hal-00932613 , version 1 (17-01-2014)

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Imen Bahri, Lahoucine Idkhajine, Eric Monmasson, Mohamed El Amine Benkhelifa. Hardware/Software codesign guidelines for System on Chip FPGA-based sensorless AC drive applications. IEEE Transactions on Industrial Informatics, 2013, 9 (4), pp.2165-2176. ⟨10.1109/TII.2013.2245908⟩. ⟨hal-00932613⟩
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